16 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF016B
Data Sheet
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF016B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-
Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 5. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signif-
icant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instructions
Address
Dummy
Data
Maximum
Instruction
Read
High-Speed
Description
Read Memory at 25 MHz
Read Memory at 80 MHz
Op Code Cycle 1
0000 0011b (03H)
0000 1011b (0BH)
Cycle(s) 2
3
3
Cycle(s)
0
1
Cycle(s)
1 to ?
1 to ?
Frequency
25 MHz
80 MHz
Read
4 KByte Sec-
Erase 4 KByte of
0010 0000b (20H)
3
0
0
80 MHz
tor-Erase 3
memory array
32 KByte
Erase 32 KByte block
0101 0010b (52H)
3
0
0
80 MHz
Block-Erase 4
of memory array
64 KByte
Erase 64 KByte block
1101 1000b (D8H)
3
0
0
80 MHz
Block-Erase 5
of memory array
Chip-Erase
Erase Full Memory Array
0110 0000b (60H)
0
0
0
80 MHz
or
1100 0111b (C7H)
Byte-Program
To Program One Data Byte 0000 0010b (02H)
3
0
1
80 MHz
AAI-Word-Pro- Auto Address Increment
1010 1101b (ADH)
3
0
2 to ?
80 MHz
gram 6
Programming
RDSR 7
EWSR
Read-Status-Register
Enable-Write-Status-Reg-
0000 0101b (05H)
0101b 0000b
0
0
0
0
1 to ?
0
80 MHz
80 MHz
ister
(50H)
WRSR
WREN
WRDI
RDID 8
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H)
0
0
0
3
0
0
0
0
1
0
0
1 to ?
80 MHz
80 MHz
80 MHz
80 MHz
or
1010 1011b (ABH)
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
0
3 to ?
80 MHz
EBSY
Enable SO to output RY/BY# 0111 0000b (70H)
0
0
0
80 MHz
status during AAI program-
ming
DBSY
Disable SO as RY/BY#
1000 0000b (80H)
0
0
0
80 MHz
status during AAI program-
ming
T5.0 25044
1. One bus cycle is eight clock periods.
?2011 Silicon Storage Technology, Inc.
9
DS25044A
08/11
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